A network processor is one example of what is more generally referred to herein as a link layer device. Such link layer devices, which can be used to implement packet-based protocols such as Internet Protocol (IP) and Asynchronous Transfer Mode (ATM), are also commonly known as Layer-3 (L3) devices in accordance with the well-known Open System Interconnect (OSI) model.
Communication between a physical layer device and a network processor or other type of link layer device may be implemented in accordance with an interface standard, such as the SPI-3 interface standard described in Implementation Agreement OIF-SPI3-01.0, “System Packet Interface Level 3 (SPI-3): OC-48 System Interface for Physical and Link Layer Devices,” Optical Internetworking Forum, 2001, which is incorporated by reference herein. A given physical layer device may comprise a multiple-port device which communicates over multiple channels with the link layer device. Such channels are also referred to herein as MPHYs. As is well known, a link layer device may be advantageously configured to detect backpressure (BP) for a particular MPHY via polling of the corresponding MPHY address on the physical layer device. The detected backpressure is used by the link layer device to provide flow control and other traffic management functions, thereby improving link utilization.
A significant problem that can arise when utilizing the SPI-3 interface standard is that the standard supports a maximum of only 256 MPHYs. Although this is substantially more than other similar interfaces, such as POS-2, it nonetheless fails to meet the requirements of many high channel count (HCC) packet-based applications. For example, consider an application involving an OC-12 (Optical Carrier 12) channelized link, which has a data rate of 12*51.84 Mbps=622.08 Mbps. In such an application, it may be desirable to provide per-DS0 access to substantially the entire OC-12 facility, comprising, for example, a total of up to 8064 DS0 channels, where DS0 (Digital Signal 0) generally denotes a 64 kbps signal. The network processor should therefore ideally support flow control for all ofthe DS0 channels. Unfortunately, the current SPI-3 interface standard falls far short of this goal.
Accordingly, a need exists for improved techniques for communicating information between a link layer device and a physical layer device, so as to facilitate backpressure detection and related traffic management functions, particularly in HCC packet-based applications.